Graphic memory devices are ahead of standard memory devices in terms of their electrical requirements. With desired clock frequencies in the gigahertz range, high speeds are expected in the semiconductor chips, unattainable with conventional bonding pad arrangements in the form of rows of signal contact areas in a central bonding channel, especially since the long rewiring lines from the central bonding channel to the peripheral sides of the memory chips have excessively high inductance values, which increase the impedance and reduce the clock frequencies. These disadvantages have even more horrendous effects when it is attempted to stack such semiconductor chips of an identical type.
For rapid access to memory data of the semiconductor chips with clock frequencies in the gigahertz range, as in the case of DDR-II (Double Data Rate II) or DDR-III (Double Data Rate III) memory chips, chip stacks are not suitable. The stacking has the effect that such semiconductor devices with a semiconductor chip stack do not achieve the “high performance” criteria for DDR-II or DDR-III memory devices and therefore have until now only allowed themselves to be stacked by sacrificing “high performance”, which leads to unacceptable values with respect to the criteria of DDR-II devices.